1. Field of the Invention
The present invention relates to a solid-state image capturing apparatus and an electronic information device, and more particularly, to an amplification type solid-state image capturing apparatus, in which a pixel section includes an amplifier circuit, with improved performance, and an electronic information device including the amplification type solid-state image capturing apparatus used therein.
2. Description of the Related Art
Typically, a common amplification type solid-state image capturing apparatus includes a pixel array section in which pixel sections (also referred to simply as pixel) with amplification function are arranged in two dimensions, and a scanning circuit disposed in the periphery of the pixel array section, where the scanning circuit reads out pixel data from each pixel.
As an example of such an amplification type solid-state image capturing apparatus, APS (Active Pixel Sensor) type image sensors are publicly known. The APS type image sensors are configured with a CMOS circuit, which is advantageous for pixels to be integrated with a peripheral driving circuit and a signal processing circuit. Among such APS type image sensors, four-transistor type image sensors, which are able to obtain high quality images, have been becoming mainstream lately.
FIG. 5 is a diagram describing a conventional four-transistor amplification type solid-state image capturing apparatus, illustrating a circuit configuration of an individual pixel (unit pixel) constituting the solid-state image capturing apparatus.
As illustrated in FIG. 5, a pixel section 110, which constitutes the conventional amplification type solid-state image capturing apparatus, includes: alight receiving section 101 for converting light to electrons; a transferring transistor 102 for transferring a signal charge generated in the light receiving section 101 to a signal charge accumulation section 103; an amplifying transistor 105 for amplifying the signal charge transferred to the signal charge accumulation section 103 to generate a signal voltage corresponding thereto; a reset transistor 104 for resetting the signal charge accumulation section 103, that is, a gate of the amplifying transistor 105, to a power supply voltage Vd; and a selecting transistor 106 for reading out an output of the amplifying transistor 105 to a read-out signal line 107. In the solid-state image capturing apparatus, a plurality of pixel sections with such a configuration are arranged in two dimensions, that is, in rows and columns, to constitute a pixel array. The read-out signal line 107 is provided for each column of a pixel section in the pixel array (hereinafter, referred to as pixel column), and all the selecting transistors of the pixel in each pixel column are connected to corresponding read-out signal lines 107. In addition, each read-out signal line 107 is connected a corresponding constant current source load 111. The constant current source load 111 is configured of a transistor connected between one terminal side of the read-out signal line 107 and a ground, and a gate of the transistor is configured to allow a control signal SW (Vc) to be input.
Herein, the light receiving section 101 is typically constituted of buried photodiodes (photoelectric conversion elements). The transferring transistor 102 is connected between the signal charge accumulation section 103 and a cathode of the photodiode, the signal charge accumulation section 103 accumulating signal charges from the light receiving section 101; and its gate is connected to a transfer gate selection line 123. The signal charge accumulation section 103 is also referred to as a floating diffusion section (FD section) 103 hereinafter. The transferring transistor 102 is turned on when a voltage level TX of the transfer gate selection line 123 is at its high level, and transfers a signal charge generated at the photodiode to the signal charge accumulation section 103.
In addition, the reset transistor 104 is connected between the signal charge accumulation section 103 and a voltage source (power supply voltage Vd), and its gate is connected to a reset signal line 122. The reset transistor 104 is turned on when a voltage level RST of the reset signal line 122 is at its high level, and resets an electric potential of the signal charge accumulation section 103 to the power supply voltage Vd. Further, the amplifying transistor 105 and selecting transistor 106 are connected in series between the voltage source (power supply voltage Vd) and the read-out signal line 107. A gate of the amplifying transistor 105 on the voltage source side is connected to the signal charge accumulation section 103. In addition, a gate of the selecting transistor 106 on the read-out signal line side is connected in series to a selection signal line 121. The selecting transistor 106 is turned on when a voltage level SEL of the selection signal line 121 is at its high level, and selects a corresponding pixel so that a signal voltage of the pixel is read out to the read-out signal line 107.
Next, the operation of the amplification type solid-state image capturing apparatus will be described.
In the light receiving section 101, a signal charge is generated by photoelectric conversion of incident light, and the signal charge generated at the light receiving section 101 is transferred to the signal charge accumulation section (FD section) 103 by the transferring transistor 102. The signal charge accumulation section 103 is reset to the power supply voltage Vd by the reset transistor 104 prior to the transferring of the signal charge from the light receiving section 101. Thus, the electric potential of the signal charge accumulation section 103, at each time after resetting and transferring the signal charge, is amplified by the amplifying transistor 105, and is read out to the read-out signal line 107 through the selecting transistor 106. At this stage, the read-out signal line 107 is supplied with an electric current from the pixel 110, in accordance with the electric potential of the signal charge accumulation section 103, and the supplied electric current is discharged to the ground side through the constant current source load 111. Thereby, a read-out voltage is generated in the read-out signal line 107 in accordance with the electric current supplied from the pixel 110, and the read-out voltage is output to circuits in a later part to obtain pixel data of each pixel.
In such a CMOS image sensor, as a pixel pitch is miniaturized from 2.2 μm to 1.75 μm, problems will arise such as decreasing of the signal charge amount due to the downsizing of the photoelectric conversion element, that is, the photodiode, and increasing of noise due to the miniaturization of the amplification type MOS transistors. For that reason, it is more effective to reduce the number of the transistors to decrease the area occupied by the transistors and increase the size of the photoelectric conversion element, rather than miniaturizing the size of the transistors. For achieving such a method, proposed is a three-transistor type pixel configuration (3TR configuration) in which a photoelectric conversion element and three transistors constitute a unit pixel.
FIG. 6 is a diagram describing a unit pixel of the 3TR configuration (hereinafter, referred to simply as pixel), illustrating a circuit configuration of two unit pixels connected to one read-out signal line.
For example, a 3TR configuration pixel section 210 includes: a light receiving section 201 consisting of photodiodes (photoelectric conversion elements); a signal charge accumulation section 203 for accumulating a signal charge from the light receiving section 201; a transferring transistor 202 connected between the signal charge accumulation section 203 and the light receiving section 201; a reset transistor 204 connected between the signal charge accumulation section 203 and reset drain wiring 225; and an amplifying transistor 205 connected between a voltage source (power supply voltage Vd) and a read-out signal line 207.
Herein, a gate of the transferring transistor 202 is connected with a transfer gate selection line 223, and the transferring transistor 202 receives a transfer pulse signal TX0 from the transfer gate selection line 223 to transfer a signal charge generated in the light receiving section 201 to the signal charge accumulation section 203. In addition, a gate of the reset transistor 204 is connected with a reset signal line 222, and the reset transistor 204 applies a voltage Vr0 of the reset drain wiring 225 to the signal charge accumulation section 203, based on by a reset signal RST0 from the reset signal line 222.
Further, similar to the 3TR configuration pixel section 210 described above, a 3TR configuration pixel section 250 includes: a light receiving section 251 consisting of photodiodes (photoelectric conversion element), for generating a signal charge by photoelectric conversion; a transfer transistor 252 for transferring the signal charge to a signal charge accumulation section 253 on the basis of a transfer pulse signal TX1 from a transfer gate selection line 273; a reset transistor 254 for applying a voltage Vr1 of reset drain wiring 275 to the signal charge accumulation section 253 on the basis of a reset signal RST1 from a reset signal line 272; and an amplifying transistor 255 for amplifying and outputting the signal voltage or the reset voltage generated in the signal charge accumulation section 253 to the read-out signal line 207.
The pixel sections 210 and 250 are connected to the read-out signal line 207 together with other pixel sections in the same column, and the read-out signal line 207 is connected to a constant current source load 211. The constant current source load 211 is configured of a transistor connected between one terminal side of the read-out signal line 207 and a ground, and a gate of the transistor is configured to allow a control signal SW (Vc) to be input.
As illustrated in FIG. 6, unlike a 4TR configuration unit pixel section, the 3TR configuration unit pixel sections 210 and 250 are not provided with a transistor that corresponds to the selecting transistor connected in series with the amplifying transistor 105 as illustrated in FIG. 5. Thus, it is not a selecting transistor in a 4TR configuration that performs a pixel selecting operation of selecting a certain pixel from among a large number of pixels connected to the read-out signal line 207, but the operation is performed by controlling an electric potential of the FD sections 203 and 253, which function as a signal charge accumulation section.
Next, the operation of the 3TR configuration unit pixel will be described.
FIG. 7 is a timing diagram illustrating one example of timing of driving pulses for driving a 3TR configuration unit pixel.
By controlling the transfer gate selection lines 223 and 273, reset signal lines 222 and 272, and reset drain wirings 225 and 275, the voltages of the FD sections 203 and 253 are changed in each pixel section, and the voltage of the read-out signal line 207 is changed accordingly.
For example, in the case of selecting the pixel section 210, the signal levels Vr0 and Vr1 of the reset drain lines 225 and 275 are set to a low-level electric potential (VL), and then the signal levels RST0 and RST1 of the reset signal lines 222 and 272 are raised and the electric potentials of the FD sections 203 and 253 are set to a low level (low reset).
Next, the constant current source load 211 of the read-out signal line 207, which corresponds to a pixel column including the pixel 210, is operated by raising the control signal SW of the transistor 211 that constitutes the constant current source load 211 (time t0). Thereafter, the electric potential Vr0 of the reset drain wiring 225, which is connected to the selected pixel section 210, is set to a high level (time t1), so that only the electric potential FD0 of the FD section 203 of the selected pixel section 210 switches to a high level. In this stage, the voltage (VFD) of the FD section 203 is defined as follows:VFD=Vd−Vth  (equation 1)
Herein, Vd denotes a power supply voltage, and Vth denotes a threshold voltage of the reset transistor 204. Accordingly, the voltage VFD of the FD section 203 becomes lower than the power supply voltage Vd, which is a disadvantage for completing electric charge transferring. With regard to this problem, a transistor with a low threshold voltage or a depletion type transistor can be used as the reset transistor 204, so that the voltage of the FD section 203 can be increased to almost as high as the power supply voltage, at the high reset time.
Thereafter, when the signal level RST0 of the reset signal line 222 of the selected pixel section 210 is dropped (time t2), an electric potential FD0 of the FD section 203 is dropped due to coupling capacitance C1 between the gate of the reset transistor 204 and the FD section 203. Further, the change in the electric potential FD0 appears in the read-out signal line 207 through the amplifying transistor 205, so that a voltage Vout of the read-out signal line 207 is also dropped, and the voltage VD0 of the FD section 203 is further dropped due to coupling capacitance C2 between the read-out signal line 207 and the gate of the amplifying transistor 205.
Owing to the effect of the two kinds of coupling capacitance, the electric potential FD0 of the FD section 203 becomes lower than the power supply voltage Vd. The voltage (reset level) Vout of the read-out signal line 207 is input to a next stage circuit (not shown) connected to the read-out signal line 207, the voltage Vout corresponding to the electric potential FD0 of the FD section 203.
Thereafter, when the transfer gate pulse (transfer pulse signal) TX0 is applied to the transferring transistor 202 (time t3 to t4), the signal charge is transferred from the light receiving section 201 to the FD section 203, causing the electric potential FD0 of the FD section 203 to drop and the voltage level Vout of the read-out signal line 207 to drop simultaneously. The voltage Vout of the read-out signal line 207 is again input in the next stage circuit. The next stage circuit obtains the difference between a reset level Vrst and a signal level Vsig to output it as a pixel signal of the selected pixel 210.
In addition, the signal level RST0 of the reset signal line 222 is switched to a high level (time t5) and the electric potential FD0 of the FD section 203 is switched to a high level, then the signal level of the reset drain wiring 225 is switched to a low level (time t6) and the electric potential of the FD section 203 is switched to a low level. Thereafter, the transistor 211, which constitutes the constant current source load, is turned off (time t7).
During such reading-out of pixel signals from the selected pixel, the voltage level Vr1 of the reset drain wiring 275 of a non-selected pixel section 250 is at a low level, and the signal level RST1 of the reset signal line 272 is at a high level. Thus, the electric potential of the FD section 253 of the non-selected pixel section 250 is fixed to the low level, in which the electric potential of the FD section 253 is not changed even if the electric potential of the read-out signal line 207 is changed.
However, when such driving is performed, the voltage of the FD section 203 after the resetting is dropped due to the coupling capacitance C1 between the gate of the reset transistor 204 and the FD section 203 and the coupling capacitance C2 between the read-out signal line 207 and the gate of the amplifying transistor 205. As a result, the electric potential difference cannot be secured sufficiently between the photoelectric conversion element (light receiving section) 201 and the FD section 203 when the transferring transistor 202 is turned on, which causes a problem of failing the complete transferring (no afterimage).
As a method for solving such a problem, Reference 1 discloses a method for boosting an electric potential of an FD section in a 3TR configuration pixel.
In the above method, it is necessary to set the width of a reset pulse for resetting the electric potential of the FD section shorter than a time for the read-out signal line 207 to follow the reset voltage of the FD section 203.
That is, the electric potential of the FD section 203 is dropped due to the coupling capacitance C1 with the gate of the reset transistor when the signal level RST0 of the reset signal line 222 is raised after the voltage Vr0 of the reset drain wiring 225 is raised and the FD section 203 reaches a reset level and before the read-out signal line 207 starts to follow. At this point, however, the read-out signal line 207 is in the middle of being raised, and therefore, the FD section 203 is boosted due to the coupling capacitance C2 between the FD section 203 and the read-out signal line 207. Thereby, the reset level of the FD section can be set high without the dropping of the electric potential of the FD section due to the coupling capacitance.
Reference 1: Japanese Laid-Open Publication No. 2005-86595